MT28EW512ABA1HPC-0SIT

MT28EW512ABA1HPC-0SIT is an asynchronous, uniform block, parallel NOR flash memory device. READ, ERASE, and PROGRAM operations are performed using a single low-voltage supply. Upon power-up, the device defaults to read array mode. The main memory array is divided into uniform blocks that can be erased independently so that valid data can be preserved while old data is purged. PROGRAM and ERASE commands are written to the command interface of the memory. An on-chip program/ erase controller simplifies the process of programming or erasing the memory by taking care of all special operations required to update the memory contents. The end of a PROGRAM or ERASE operation can be detected and any error condition can be identified. The command set required to control the device is consistent with JEDEC standards.

• 2.7V to 3.6V supply voltage (VCC)
• 512Mb density, single die stack
• 2nd generation, high lock structure
• Standard default security, single-level cell (SLC) process technology
• BLANK CHECK operation to verify an erased block, program/erase suspend and resume capability
• Word/byte program: 25us per word (typ), block erase (128Kb): 0.2s (typ)
• JESD47-compliant, 100,000 (minimum) ERASE cycles per block, data retention: 20 years (TYP)
• Unlock bypass, block erase, chip erase, and write to buffer capability
• Volatile protection, non-volatile protection, password protection
• Industrial operating temperature range from -40°C to +85°C, package style is 64-ball LBGA