MT28EW128ABA1LJS-0SIT

MT28EW128ABA1LJS-0SIT is a parallel NOR flash embedded memory. The device is an asynchronous, uniform block, parallel NOR Flash memory device. The READ, ERASE, and PROGRAM operations are performed using a single low-voltage supply. Upon power-up, the device defaults to read array mode. The main memory array is divided into uniform blocks that can be erased independently so that valid data can be preserved while old data is purged. The device supports asynchronous random read and page read from all blocks of the array. It also features an internal program buffer that improves throughput by programming 512 words via one command sequence. A 128-word extended memory block overlaps addresses with array block 0. Users can program this additional space and then protect it to permanently secure the contents. The device also features different levels of hardware and software protection to secure blocks from unwanted modification.

• Single-level cell (SLC) process technology
• Supply voltage: VCC = 2.7–3.6V (program, erase, read), VCCQ = 1.65 - VCC (I/O buffers)
• Word/byte program: 25us per word (TYP)
• Block erase (128KB): 0.2s (TYP)
• Unlock bypass, block erase, chip erase, and write to buffer capability
• CYCLIC REDUNDANCY CHECK (CRC) operation to verify a program pattern
• VPP/WP# protection– protects first or last block regardless of block protection settings
• JESD47-compliant, 100,000 (minimum) ERASE cycles per block, data retention: 20 years (TYP)
• 128Mb density, x8, x16 configuration
• 56-pin TSOP package, -40°C to +85°C operating temperature range