NEXPERIA 74LVC74APW-Q100J

74LVC74APW-Q100J is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (n active-low SD) and (n active-low RD) inputs, and complementary nQ and n active-low Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. This product has been qualified to the automotive electronics council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V).