MICRON MT41K256M16TW-107 IT:P

MT41K256M16TW-107 IT:P is a DDR3L SDRAM (1.35V) is a low voltage version of the DDR3 (1.5V) SDRAM. DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is centre-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. It features Self refresh temperature (SRT), Automatic self refresh (ASR), write levelling, multipurpose register, output driver calibration.