CY2308SXI-1

CY2308SXI-1 is a CY2308 3.3V zero delay buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL that locks to an input clock presented on the REF pin. The PLL feedback is driven from external FBK pin, so user has flexibility to choose any one of the outputs as feedback input and connect it to FBK pin. The input-to-output skew is less than 250ps and output-to-output skew is less than 200ps. The input clock is directly applied to the output for chip and system testing purposes by the select inputs. It accepts the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is less than 700ps.

• Output frequencies equal the reference if there is no counter in the feedback path
• Zero input-output propagation delay, adjustable by capacitive load on FBK input
• Multiple low skew outputs
• Two banks of four outputs, three-stateable by two select inputs
• 10MHz to 133MHz operating range
• 75ps typical cycle-to-cycle jitter (15pF, 66MHz)
• Industrial temperature range from –40°C to +85°C
• 16-pin SOIC package