ALLIANCE MEMORY AS4C64M8D2-25BIN

AS4C64M8D2-25BIN is a 512M – (64M x 8bit) DDRII synchronous DRAM (SDRAM). The 512Mb DDR2 SDRAM is a high-speed CMOS double-data-rate-two (DDR2), synchronous dynamic random-access memory (SDRAM) containing 512Mbits in an 8-bit wide data I/Os. It is internally configured as a quad bank DRAM, 4 banks x 16Mb addresses x 8 I/Os. The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, write latency = read latency -1, and on-die termination (ODT). All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS#) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in RAS #, CAS# multiplexing style.