RENESAS RC32312A-EVK

RC32312A-EVK is an evaluation kit used to demonstrate and evaluate the RC32312A, a fully integrated clock synthesizer/generator and clock jitter attenuator. The kit can evaluate major parameters including phase noise, spurious attenuation, clock frequency, output skew, phase alignment, device timing, and the signal waveform. The device on the board accepts any input frequency from 1KHz to 1GHz. The RC32312A consists of a single APLL and DPLL design that allows for two separate frequency domains. The APLL can be used independently of the DPLL to generate synthesized clocks at the outputs that track the frequency of the input at the XIN pin. The DPLL can be used for jitter attenuation, clock filtering, and frequency translation while tracking clocks from the CLKIN pins. The DPLLs provide a programmable bandwidth and a DCO function for real-time frequency/phase adjustment.