NXP LPC54618J512ET180E

LPC54618J512ET180E is a 32bit ARM Cortex-M4 microcontroller. It offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point processor is integrated into the core. It features a programmable PMU (power management unit) to minimize power consumption and to match requirements at different performance levels. It has an ultra-low power micro-tick timer, running from the watchdog oscillator that can be used to wake up the device from low power modes.