MICRON MT41K512M16VRP-107 IT:P

MT41K512M16VRP-107 IT:P is a TwinDie 1.35V automotive DDR3L SDRAM. It is a high-speed, CMOS dynamic random access memory device internally configured as two 8-bank DDR3L SDRAM devices. The DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK.